1. Field of the Invention
The present invention relates to digital to analog converters and, more particularly, to a digital to analog converter which can suppress "glitches" such as transient spikes and overshoots that would otherwise appear in the converter's analog output as a result of transistions in the digital input.
2. State of the Prior Art
Various digital to analog (D/A) converters have been heretofore proposed for producing an analog output from a digitally coded signal with high speed. One such converter may be comprised of a plurality of current switches, one for each bit of a digitally coded signal, which may be connected to a resistance ladder network for providing binary weighting of currents from the switches. In a typical D/A converter 10 as shown in FIG. 1, a control circuit 12 may be provided having four input terminals adapted to receive four digital input bit signals of a digital input signal. These digital input bit signals may be supplied to corresponding current switches 14, 16, 18 and 20 to selectively control the switching thereof. Each current switch may be connected to receive a reference current from a corresponding constant current source 22, 24, 26 or 28 and may have its ouput terminal connnected to a corresponding input port of an R-2R ladder network 30. The R-2R ladder network 30 may have an output port 32 which also serves as the input port associated with the most significant bit. Each current switch may have stray capacitance 36, 38, 40 or 42 between its output terminal and ground.
More specifically, the constant current sources 22 through 28 may be connected to a DC voltage supply line designated as +Vcc to receive a reference current therefrom. Each current switch may have two branches between which the reference current is steered to flow into the resistive ladder 30 or ground in response to a corresponding digital input bit signal. That is, when the digital input bit signal is at a first voltage level or at a logic 1, the current switch may be rendered conductive allowing the reference current to flow from the corresponding constant current source to the resistive ladder. On the other hand, when the bit is at a second level or at a logic 0, the current switch may be rendered nonconductive passing the reference current to ground.
The switches 14 through 20 may usually be high speed current switches which are comprised of bipolar transistors or FET's. FIG. 2 shows a typical example of prior art current switch which includes a pair of switching trransistors Q1 and Q2 arranged in left and right hand circuit branches, respectively. The switching transistor Q1 may have its emitter connected to the output of the constant current source 22, 24, 26 or 28 and its collector connected to a corresponding input port of the resistive ladder 30. The switching transistor Q2 may be connected at its emitter to the constant current source and at its collector to ground. The input to the base of transistor Q2 may be a digital input bit or logic input signal which controls the balance of flow of the reference current from the constant current source. The input to the base of transistor Q1 may be logic reference signal +Vbb which sets the threshold at which the circuit becomes unbalanced, allowing the logic input signal to change the balance of current flow from one branch of the circuit to the other. The reference current I is thereby steered between the transistors Q1 and Q2, pulling the current either to the resistive ladder 30 or to ground. When the logic input signal is at a logic 1, the transistor Q2 may turn off while the transistor Q1 may turn on, thus directing the reference current I through the left hand circuit branch to the resistive ladder 30. When a logic 0 input signal turns on the transistor Q2 and turns off the transistor Q1, the reference current from the constant current source may be supplied to ground.
Referring back to FIG. 1, the resistance network 30 may be a resistive ladder of the conventional R-2R configuration, as described above, which provides binary weighting of reference currents from the current switches 14, 16, 18 and 20. This network may have a plurality of resistors of value R, designated by reference numerals 50, 52 ane 54, each being connected between two adjacent ones of the input ports of the network. The input ports associated with the least and most significant bits may also have connected thereto another resistors of value R, designated by 56 and 58, respectively, which resistors may also be connected to ground. The remaining input ports of the network may be connected to ground through resistors of value 2R, designated by 60 and 62. With this arrangement, the network 30 decrements each reference current received from a corresponding current switch by a factor of 2 as it flows toward the output port 32. Since the input port associated with the most significant bit serves as the output port of the network, it is seen that the reference current supplied thereto carries the most weight of all the reference currents I from the current switches 14, 16, 18 and 20. All the decremented reference currents are summed as they flow toward the output port 32 to form the analog output thereat.
One of the problems associated with this conventional D/A converter is that the stray capacitance of each current switch occurring between its output terminal and ground due to the parasitic collector-base capacitance of its associated switching transistor need to be charged or discharged to accomplish switching in either direction, which would result in "glitches" in the converter output. Referring to FIGS. 3 and 4, the converter error, or glitches, due to the parasitic capacitance can be illustrated as follows: When the digital input bit signals change from 0000 to 0001, only the current switch 14 may be turned on while the remaining switches may be kept off. Assuming the absence of the stray capacitance in each current switch involved, each input port of the resistive ladder 30 would rise to a corresponding predetermined value in a step fashion. However, in actuality, each current switch has stray capacitance so that the resulting integrating action delays the rise of each input port voltage Va through Vd as shown in FIG. 3. The voltage at input port a will eventually reach a level indicated by I.times.2/3R, under the progressively less influence of the stray capacitances 36, 38, 40 and 42 in the order named. As is well known, the R-2R ladder network functions to decrement each reference current by a factor of 2 per stage. Accordingly, the voltages Va, Vb, Vc and Vd at input ports a, b, c and d, respectively, will rise and settle at the respective values as shown in FIG. 3.
When the digital input signal changes from 0000 to 1000, the current switch 20 may be turned on, so that the voltage of the same waveform as Va in FIG. 3 will appear at input port d. Hence, it is seen that a single bit input transition will cause variations in the time delay involved in bringing about voltage changes at the output port 32, depending upon which of the input bits makes a transition.
It will now be understood that this differential time delay associated with each bit is the cause of glitches like one 70 appearing V1, as shown in FIG. 4. FIG. 4 shows the manner in which the voltage at the output port 32 will change with a transition of the digital input from 0111 to 1000. In this Figure, voltage V2 may be the one developed at the output port when the current swtich 20 turns on, and the voltage rises gradually to I.times.2/3R. The other voltage V3 may also be the one appearing at the output port 32, which reflects the turn off of the remaining current switches 14, 16 and 18. The resultant analog output voltage V1 is the sum of the voltages V2 and V3.
As seen, the resulting voltage V1 has a glitch or transient spike occurring above the level of I.times.2/3R, and it is desirable to suppress such glitches to increase the compliance of the analog output voltage with a corresponding digital input.
It is therefore an object of the present invention to provide an improved digital to analog converter with a view to overcoming the above-said disadvantages or prior art device.
Another object of the present invention is to provide an improved digital to analog converter that can suppress glitches such as transient spikes and overshoots that would otherwise appear in the converter's analog output as a result of transitions in digital input bit signals.
A further object of the present invention is to suppress glitches appearing in the analog output of a digital to analog converter simply by incorporating compensating capacitors into a resistive ladder without requiring an additional glitch suppressor provided at the output of the converter.